1. Field of the Invention
The present invention relates to an interconnection structure between a signal line and a thin film transistor capable of achieving high aperture rate and high definition, and applicable to TFT array substrates for display devices such as liquid crystal displays and organic electroluminescence (EL) display devices.
2. Description of the Related Art
As disclosed in JP2004-341185A for example, a conventional liquid crystal display device comprises scanning lines, signal lines, pixel electrodes, thin film transistors that include a gate electrode connected to a corresponding scanning line in proximity to each point of intersection of a scanning line and a signal line, a drain electrode connected to a corresponding signal line, and a source electrode connected to a pixel electrode, storage capacitor lines a part of which is overlapped with a pixel electrode to form a storage capacitor, a counter electrode, and liquid crystal placed between each pixel electrode and counter electrode.
In each thin film transistor, pairs of a source electrode, which is connected to a pixel electrode, and a drain electrode, which is connected to a signal line, are arranged in the scanning line array direction. The source electrode is integrated with a pedestal, which extends along the scanning line, thus forming a single layer, and the pedestal and the pixel electrode are connected via a contact hole created on an insulating layer on the pedestal, and as a result, the pixel electrode is connected to the source electrode.
In such a liquid crystal display device, a plurality of storage capacitor lines are formed on a plurality of scanning lines and signal lines via a first insulating film, with storage capacity units of each storage capacity line covering corresponding pairs of a scanning line and a signal line. On those storage capacity units, a plurality of pixel electrodes is formed via a second insulating film. The above structure allows a plurality of scanning lines, signal lines, and thin film transistors to be installed overlapped with a plurality of pixel electrodes, narrowing the space between each pixel electrode up to the processing limit and thus achieving high aperture rate.
In the liquid crystal display device disclosed in JP2002-98993A, three pixel electrodes (R, G, B) constituting a pixel are placed in positions of vertices of an isosceles triangle. These pixel electrodes are installed displaced from each other, with a source electrode, gate electrode, and drain electrode of each thin film transistor installed column-wise, and the drain electrode protruding from the signal line in the row direction. This structure allows an L-shaped groove, for example, to be formed in the vicinity of each source electrode when the pixel electrode and the signal line are connected. When the drain electrode, signal line, and source electrode are formed, the existence of a photoresist film deepens these L-shaped grooves to some extent. When a metal film is etched with the photoresist used as a mask, etchant tends to stay in the L-shaped grooves, which may cause improper processing, and in the worst case, the signal line including the drain electrode and the source electrode may be short-circuited.
As disclosed in JP2002-98993A, to prevent L-shaped grooves from being formed, the side edge of signal lines of a liquid crystal display device is used as a drain electrode, and a source electrode is formed linearly in the direction of the scanning lines to the drain electrode. This prevents retention of etchant used for metal film etching with a photoresist film used as a mask when a drain electrode, signal lines connected to the drain electrode, and a source electrode are formed. Improper processing and short circuit between the drain electrode and the source electrode can thus be prevented.
Meanwhile, in a liquid crystal display device disclosed in JP2004-341185A, to achieve higher definition, the pitch of scanning lines and that of signal lines are further reduced. If the pitch of adjacent signal lines is reduced to below 20 μm for example, it becomes infeasible to linearly install the source electrode and drain electrode of a thin film transistor between adjacent signal lines in the direction of scanning lines.
The structure of a liquid crystal display device 1 shown in FIG. 7 solves this problem. The liquid crystal display device 1 comprises scanning lines 2 arranged in rows, signal lines 3 arranged in columns, thin film transistors 4 installed in each region defined by scanning lines 2 and signal lines 3, a pixel electrode 5 connected to the source electrode 4a of each thin film transistor 4 via a contact hole, and a storage capacitor electrode 6 installed between the pixel electrode 5 and a scanning line 2/signal line 3 via an insulating film (not shown).
To reduce the space between adjacent signal lines 3, the source electrode 4a and the drain electrode 4b of each thin film transistor 4 are installed in the direction of signal lines 3, and the gate electrode 4c of each thin film transistor 4 integrates a part of the scanning line 2. The part of the signal line 3 that crosses the scanning line 2 forms an L-shaped connecting portion 3a in a plan view, with the signal line 3 having thick line width extending over to the gate electrode 4c. The edge of the connecting portion 3a that protrudes from the signal line 3 in the longitudinal direction of the scanning line 2, namely drain electrode 4b, is integrated with the signal line 3. Since the L-shaped connecting portion 3a forms a concave area 4g surrounded on three sides when the signal line 3 including the connecting portion 3a and the drain electrode 4b are etched, etchant and washing liquid used after etching retain in the concave area 4g as in the case disclosed in JP2002-98993A, thus causing improper processing or insufficient drying.
In the liquid crystal display device 1, since the gate electrode 4c is formed integrating a part of the scanning line 2, and thus the pitch between signal lines is small, it is infeasible to apply the structure disclosed in JP2002-98993A to eliminate the emergence of a concave area 4g. Although the line width is made as small as 3 μm for example to minimize the pitch of signal lines 3, the area in proximity to the intersection of the signal line 3 and the scanning line 2 is bulging because the scanning line 2 is installed orthogonal to the signal line 3. Since the signal line 3 is formed over the scanning line 2, the connecting portion 3a along the longitudinal direction of the signal line 3 must remain wide to prevent a so-called disconnection caused by steps. Therefore, the space reduction of signal lines 3 is restricted.
The above-mentioned problem also arises with a liquid crystal display device in which a drain electrode and a source electrode of each thin film transistor are installed reversely, namely the source electrode is connected to a signal line and the drain electrode is connected to a pixel electrode.